MCM Layout with Distributed-RLC Model
نویسنده
چکیده
,/ This paper models high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is consequently established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector's performance and its geometrical parameters. The study leads to an A-tree topology to optimize the defined performance-driven layout problem. Significant improvement, an average up to 67% reduction on the interconnection delay, is achieved over large sample of MCM designs, as compared with the well known Steiner tree topology. The result presented in this paper is the first to place the layout design on the sophisticated RLC model as well as to demonstrate the significant impact of the underlying circuit model on the layout design.
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